Chip-8 on the COSMAC VIP: Loading and Saving Variables

This is part of a series of posts analysing the Chip-8 interpreter on the RCA COSMAC VIP computer. These posts may be useful if you are building a Chip-8 interpreter on another platform or if you have an interest in the operation of the COSMAC VIP. For other posts in the series refer to the index or instruction index.

INSTRUCTION GROUP: 6XNN
Load VX with NN

These instruction groups are used for loading or saving the Chip-8 variables.

Instruction group 6XNN is very straightforward. It simply copies the second byte of the instruction into VX.

Here’s the code for this routine:

Execution time for this instruction is 6 machine cycles (27.24 microseconds)

Instruction group 8XY0 is part of the broader 8XYN group. These are largely arithmetic and logic instructions, the exception being this sub-group, which copies the value in VY into VX. Here’s the code:

Execution time for this instruction is 12 machine cycles (54.48 microseconds)

Register A on the CDP1802 is used as a general memory pointer by Chip-8. For the purpose of Chip-8 programmes it is designated as the variable I. Although RA can potentially point anywhere within the 64K that is addressable by the CDP1802, for Chip-8 programmes I is restricted to the first 4K (This is the maximum amount of on-card RAM for the COSMAC VIP). This variable can be set with the instruction AMMM where MMM is a 12-bit address from 0x000 to 0xFFF. To form the address, the interpreter uses the low-order byte of the instruction as it is and masks the high order byte so that the first hex digit is replaced with 0x0. So, for example, the instruction AD08 would set I to point to address 0x0D08.

Here’s the code:

Execution time for this instruction is 12 machine cycles (54.48 microseconds)

The next two instructions are part of a miscellaneous collection of FXXX instructions. These have a second decoding stage. The second byte of these instructions is actually the low-order byte of the address of their handling routines. The second stage decoding simply grabs this byte and uses it to update the interpreter’s programme counter so it continues execution from the correct point. Here’s the code for this second stage decoding:

This second stage of decoding adds an overhead of 4 machine cycles (18.16 microseconds) to group FXXX instructions.

Here’s a flowchart for both of these instruction groups:

Now here’s the code for the first of those instruction groups, FX55, which stores variables V0 through VX in memory starting from the address pointed to by I.

The execution time for this instruction is 14 machine cycles (63.56 microseconds) plus 14 machine cycles for each variable stored. Total execution time will therefore range from 28 machine cycles (127.12 microseconds), if you store only V0, to 238 machine cycles (1080.52 microseconds), if you store all 16 variables.

One important thing to note about this routine is that I is not reset. At the end of the routine I will be pointing to the byte after the location of the last value stored. Another thing worth noting is that there is no validation of the address – the Chip-8 programmer must ensure that the address used here is sensible and there is sufficient space above it to store all the requested variables.

Finally, here’s the code for the complementary routine, FX65, which loads the values starting at the address in I into variables V0 through VX:

The execution times for this instruction are identical to FX55. Once again note that I is left pointing to the address following the last one read into a variable.

A contemporary interpreter should implement all these instruction groups.